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The Micron Semiconductor, Inc. patent solves the following problem:
Increasing pin counts, as well as faster circuit speeds, made the need for reliable ESD protection integrated circuits (ICs). Input / output signal to a complimentary metal oxide semiconductor (CMOS) circuit usually fed to the input / output pads connected to the gate metal oxide semiconductor (MOS) transistors. If high voltage static discharge accidently applied to any of the input / output pins of an IC, the input / output transistor gate insulator and the contact between the pad and the underlying active area is vulnerable to damage if adequate ESD protection not now. Therefore, all the pins of the mos ICS must ESD protected to prevent any harmful static discharge voltages from damaging the IC.
Our analysis of this patent is as follows:
Micron Semiconductor, Inc.’s patent US 5218222 A deals with Output ESD protection circuit.
The first part of the protection circuit output ESD present invention comprises a low resistance connected in series between an output pad and conventional active output pad pullup and pulldown driver. In a preferred photo, a polysilicon resistor connected in series between an output pad and a metal bus. Metal bus, a lateral bipolar device connected like an n-channel pulldown an output node and a common potential (conventionally labeled as ber). The pullup device is also an active n-channel pullup device connected between an operating potential (conventionally labeled as VCC) and the output node. The two drains of two n-channel devices with n-man under the n + diffusion area where the metal contacts are formed to prevent the metal also increases the substrate during an ESD event. This circuitry combination provides ESD protection equal to or greater than the voltage range of + 8000 / -2000 V for HBM solution (Mil. STD. Human body model [HBM] test model) as well as protection similar to or greater than the voltage range of + 900 / -700 V for MM EIAJ solution (EIAJ machine model [MM] test model). The concept of using a low resistance between a pad and the related active devices (ie, ESD protection circuitry) working in combination with other ESD protection circuitry layouts and work as good as the input pad ESD protection.
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